FIG. 1 illustrates basic components of an image display system utilizing a MEMS device spatial light modulator (SLM) for the projection of images. Light from a light source is directed onto an array of pixel modulator elements whose positions are individually settable in synchronization with image data and with the incident light either to direct light onto an imaging surface through a projection lens (when in the “ON” position) or to block or direct light away from the imaging surface, such as to a light absorber (when in the “OFF” position). For simplicity of illustration, FIG. 1 illustrates an array with just two modulator elements; however, a typical array will have 1000's of such elements arranged in rows and columns, with individual elements having a correspondence with pixel positions of a projected image.
FIGS. 2 and 3 illustrate the structure of a conventional pixel modulator element in the form of a micromirror like that employed in an array of micromirrors in a device such as a Texas Instruments DLP® digital micromirror device (DMD). A DMD is a digitally controlled optical MEMS device. When coupled with a source of illumination and suitable optical system components, the DMD may be used to modulate the amplitude and/or direction of incoming light for creating images or other light patterns. The DMD may be used for light modulation for display of images. Other uses of a DMD include structured light, augmented reality, microscopy, medical instruments, spectroscopy, machine vision, industrial inspection, 3D scanning, 3D optical metrology, automated fingerprint identification, face recognition, interactive display, information overlay, chemical analyzers, photo-stimulation, virtual gauges, and many other applications. The DMD may be used in systems providing image projection as well as in systems providing image capture, or both image projection and image capture. Light sources which may be modulated by a DMD include Xenon lamps, laser light sources, LEDs and phosphor emissions.
A typical DMD comprises a micromirror array, a memory array, a data & controller receiver and a micromirror array reset control. The micromirror array typically comprises many 100,000's (sometimes 1 million or more) reflective, individually positionable digitally switchable, micrometer-sized mirrors organized in a two dimensional n column×m row or other systematically arranged array. The array may have a rectangular Manhattan-type pixel configuration with rectangular mirror elements having edges aligned with sides of the array rectangle as shown in FIGS. 4 and 5, or may have a diamond pixel configuration with diagonals aligned with sides of the array rectangle as shown in FIGS. 6 and 7. In the Manhattan-type configuration, the columns of each odd row are in pixel-to-pixel column alignment with the columns of each adjacent even row. In the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns of the adjacent even row.
Conventional micromirrors may be aluminum elements approximately 5-10 microns in size (e.g., 7.6 micron pitch) and switchable between discrete angular positions of +12 deg. (“ON” state) to −12 deg. (“OFF” state) relative to a 0 deg. flat reference state when mirrors are parked in an inactive state, parallel to the plane of the array (see FIGS. 5 and 7). The parked position is not a latched position. The individual micromirror angular positions are relatively flat, but will vary. The tilt direction is perpendicular to the hinge-axis. The “ON”-state position is directed toward one side of the package, the “OFF”-state position is directed to the other side of the package.
The memory array is typically a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of n memory cell columns×m memory cell rows. The memory array is addressed on a column-by-column basis, over a double data rate (DDR) bus. The DMD is typically used in conjunction with a digital controller chip. Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a particular mirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents after the mirror clocking pulse is applied. The angular position (+12 deg. or −12 deg.) of the individual mirror changes synchronously with the micromirror clocking pulse, rather than being coincident with the memory cell data update. Thus, writing a logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding mirror switching to a +12 deg. (“ON”-state) position, and writing a logic 0 into a memory cell following by a mirror clocking pulse results in the corresponding mirror switching to a −12 deg. (“OFF”-state) position. Updating the angular position of the mirror array is done in two steps. First, updating the contents of the memory. Second, application of a mirror reset to all or a portion of the mirror array (depending on the configuration of the system). Mirror reset pulses are generated internally by the DMD chip, with the application of the pulses being coordinated by the controller.
The conventional DMD micromirror pixel modulator element is an electro-mechanical element that operates with two stable mirror states (+12 deg. and −12 deg. for current DMDs) that are determined by electrostatics of the pixel during operation. Which of the two positions the mirror is placed in determines the direction that light incident on the array is deflected. By convention, the positive (+) state is tilted toward the illumination and is referred to as the “ON” state, and the negative (−) state is tilted away from the illumination and is referred to as the “OFF” state. FIG. 5 shows a pixel in the “ON” and “OFF” states for an array having micromirrors arranged in a Manhattan-type configuration. FIG. 7 shows a pixel in the “ON” and “Off” states for an array having micromirrors arranged in a diamond-type configuration. In each case, the mirror in the “ON”-state position directs light incident from the illumination light path toward the projected light path (viz., toward the projection lens in the display system of FIG. 1), and the mirror in the “OFF”-state position directs the light incident from the illumination light path toward the off-state light path (viz., toward the light absorber in FIG. 1).
In the conventional Manhattan-type configuration illustrated in FIGS. 4 and 5, incident illumination is directed diagonally relative to the array (from upper left to lower right in the example given in FIGS. 4 and 5). The mirrors are generally rectangular elements arranged to tilt about a hinge axis extending at 45 deg., diagonally of the mirror and perpendicular to the direction of incident illumination. In the conventional diamond-type configuration illustrated in FIGS. 6 and 7, incident illumination is directed parallel to one of the rows and columns relative to the array (from left to right parallel with the offset rows in the example given in FIGS. 6 and 7). The mirrors are generally rectangular elements arranged to tilt about a hinge axis extending parallel to the other of the rows and columns and perpendicular to the direction of incident illumination.
A side-by-side comparison of the diamond and Manhattan arrangement is illustrated in FIG. 8. As is apparent from the comparison, the diamond arrangement utilizes micromirror pixels similar to those of the Manhattan arrangement, except rotated 45 deg.
Mechanically the pixel is comprised of a mirror attached by means of a via support to a hidden yoke and a torsional hinge as shown in FIGS. 2 and 3. The yoke makes contact with the surface below on the spring tips. FIG. 2 shows a mirror in each of the two stable states. The electrodes shown are used in electrostatically holding the mirror in these positions. Below each mirror is a memory cell formed from Dual CMOS memory elements as depicted in FIG. 3.
The state of the two memory elements of the memory cell are not independent, but are always opposite. If one element is 1 the other element is 0, and vice versa. The state of the pixel memory cell plays a part in the mechanical position of the mirror; however, loading the memory cell does not automatically change the mechanical state of the mirror. Although the state of the dual CMOS cell plays a part in determining the state of the mirror, it is not the sole factor. Once the mirror has landed changing the state of the memory cells will not cause the mirror to flip to the other state. Therefore, memory state and mirror state are not directly linked together.
In order for the state of the CMOS memory to be transferred to the mechanical position of the mirror, the pixel must undergo a “Reset”. This Reset momentarily releases the mirror and then re-lands the mirror based on the state of the CMOS memory below. For this reason, data sheets typically specify a period of time prior to Reset during which the memory cell should not be loaded, and also specify a period of time after a Reset has occurred before new data is to be loaded. A Reset allows groups of pixels to be pre-loaded and then change their mechanical position simultaneously.
Examples of conventional MEMS devices employing micromirrors are described in U.S. Pat. Nos. 7,011,415 and 7,404,909 and in US Patent Pub. No. US 2009/0067025, the entireties of all of which are incorporated herein by reference.
The dimensions of the DMD array are determined by the resolution of the particular DMD. For example, a DMD with an XGA resolution may have pixels configured in an array of 1024 columns×768 rows. For the purpose of resetting and block clearing, the DMD may be divided into blocks. For example, XGA devices are typically divided into 16 blocks of 48 rows each. DMD memory is typically loaded by row, with an entire row loaded even if only one pixel in the row needs to be changed.
The DMD is typically fabricated as a MEMS component containing an array of aluminum micromirrors atop a CMOS substrate that digitally switch in a binary state. A typical configuration includes a uniform band of border micromirrors (referred to as a “pond”) around the perimeter of the a central core of active micromirrors in the array. These border micromirrors are not user-addressable but are tilted into the −12 deg. (“OFF”) position once power has been applied to the device. An example known implementation has 10 border mirrors on each side of a 912×1140 active mirror array. The border mirrors serve the purpose of directing stray incident light out of the field of view of the projected light path.
Optimal, long-term performance of a DMD device can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), case temperature, ambient humidity (storage and operating), and power on/off duty cycle. “Landed duty-cycle” refers to the percentage of time an individual micromirror spends landed in one state (+12° or −12°) versus the other state (−12° or +12°). It does not account for the effect of micromirror switching duty cycle, which is application dependant. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
Processing of the digital input image and conversion of the data into a format usable by the DMD is performed by the controller. The DMD steers light by using binary pulse-width modulation (PWM) for each micromirror. In a typical application 24-bit RGB data is received at a display device at 120 Hz frame rate. This frame rate is composed of three colors (red, green, blue), with each color equally divided in the 120 Hz frame rate. Thus, each color has a 2.78 ms time slot allocated for display within the available frame display time. Because each color has an 8-, 9-, or 10-bit depth, each color time slot is further divided into bit-planes. A bit-plane is the two-dimensional (2D) arrangement of 1-bit data extracted from all the pixels in the full color 2D image to implement dynamic depth. The length of each bit-plane in the time slot is weighted by a corresponding power of two of its binary representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of the weight of all bit planes in the time slot equal to 256. Therefore, a single video frame is composed of a series of bit-planes as illustrated in FIG. 9. Because the DMD mirrors can be either “ON” or “OFF” depending on their tilt angle settings, an image is created by turning “ON” the mirrors corresponding to the bits set to logic 1 in a bit-plane and “OFF” the mirrors corresponding to the bits set to logic 0 in that bit-plane. With binary pulse-width modulation, the intensity level of the color at a particular image pixel location is reproduced by controlling the amount of time the mirror is “ON” for that pixel. For a 24-bit RGB frame image inputted to a typical DMD array controller chip such as a Texas Instruments DLPC350, for example, 24 bit planes are created and stored in a double-buffered eDRAM embedded in the chip, which sends them to the DLP4500 DMD device, for example, one bit-plane at a time. Depending on the bit weight of the bit-plane, the DLPC350 controls the time this bit-plane is illuminated, controlling the intensity of the bit-plane.
FIG. 10 illustrates the weighted illumination times for the bit-planes in a pulse-width modulation scheme employing simple binary weighting. To improve image quality in video frames, these bit-planes, time slots, and color frames are typically shuffled and interleaved with spatial-temporal algorithms by the controller chip to avoid undesirable motion artifacts and other similar anomalies. For applications where video enhancement is not desired, the video processing algorithms can be bypassed and replaced with specific sets of bit-planes. The bit-depth of the pattern is then allocated into the corresponding time slots. Furthermore, an output trigger signal is also synchronized with these time slots to indicate when the image is displayed. For structured light applications, this mechanism provides the capability to display a set of patterns and signal a camera to capture these patterns overlaid on an object. US Patent Pub. No. 2007/0064008, incorporated herein by reference, includes a description of example schemes for division of an image frame display period into weighted time slices to display an image using incident light pulse-width modulation to control pixel color and intensity.
A functional block diagram of the Texas Instruments DLPC350 chip is shown in FIG. 11. The DLP350 chip stores two 24-bit frames in its internal memory buffer. This 48 bit-plane display buffer allows the DLPC350 to send one 24-bit buffer to the DMD array while the second buffer is filled from flash memory or streamed in through the 24-bit RGB interface. In streaming mode, the DMD array displays the previous 24-bit frame while the current frame fills the second 24-bit frame of the display buffer. Once a 24-bit frame is displayed, the buffer rotates, accessing the next 24-bit frame to the DMD. Thus, the displayed image is a 24-bit frame behind the data streamed through the 24-bit RGB parallel interface. In structured light mode, the 48 bit-planes can be pre-loaded from flash memory and then sequenced with a combination of patterns with different bit depths.
The Texas Instruments DLP5500 DMD is an example of a digitally controlled MEMS spatial light modulator (SLM) that, when coupled to an appropriate optical system, can be used to modulate the amplitude, direction, and or phase of incoming (illumination) light. Architecturally, the DLP5500 is a latchable, electrical-in, optical-out semiconductor device (micro electro-optical-mechanical system or MEOMS). The DLP5500 is one of three components in the Texas Instruments DLP 0.55 XGA chip-set. Other components of the chip-set are the Texas Instruments DLPC200 and DLPA200 which control and coordinate the data loading and micromirror switching. Electrically, the DLP5500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a square grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is written to on a column-by-column basis, over a 16-bit Low Voltage Differential Signaling (LVDS) double data rate (DDR) bus. The micromirror array is organized in a Manhattan-type two-dimensional array of 1024 micromirror columns by 768 micromirror rows, each mirror having an associated respective memory cell. The mirrors are aluminum reflective elements of approximately 10.8 microns in size, tiltable about a hinge axis for switching between two discrete angular positions: −12 deg. and +12 deg. The angular positions are measured relative to a 0 deg. “flat state”, which is parallel to the array plane. The tilt direction is perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The “ON”-state landed position is directed towards the “Row 0, Column 0” corner of the device package (upper left corner in FIGS. 4 and 5). The “OFF”-state landed position is directed towards the “Row 767, Column 1023” corner of the device package (lower right corner in FIGS. 4 and 5). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred to as “XGA”.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror “clocking pulse” is applied. The angular position (−12 deg. or +12 deg.) of the individual micromirrors changes synchronously with a micromirror “clocking pulse”, rather than being synchronous with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror reset will result in the corresponding micromirror switching to a +12 deg. position. Writing a logic 0 into a memory cell followed by a mirror reset will result in the corresponding micromirror switching to a −12 deg. position. Operationally, updating the angular position of the micromirror array consists of first updating the contents of the CMOS memory, followed by application of a mirror “Reset” to all or a portion of the micromirror array (depending upon the configuration of the system). Mirror Reset pulses are generated by the DLPA200, with application of the pulses being coordinated by the DLPC200 controller. Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the −12 deg. position once power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array.
FIG. 12 shows a top view of a Texas Instruments DLP® DMD having a 1024 column×768 row array of micromirrors in a Manhattan-type arrangement. Each individual mirror and underlying structure corresponds to one image forming pixel (picture element) for modulating incident light for imaging color and intensity of a corresponding pixel of a displayed image. FIG. 12 also illustrates a cross-section taken along the diagonal hinge axis showing the construction of the pixel element. The MEMS mirrors at each pixel position are formed as a superstructure over a silicon chip which has been processed using CMOS processing steps to form the memory array. The CMOS circuitry comprises transistors (doped silicon), contacts and interconnects (patterned Metal 1, Metal 2 layers). Contacts to the underlying CMOS circuitry (“Via 2 Contact to CMOS”), metal address pads, and bias/reset bus elements (see FIG. 3) are formed through deposition and patterning of a conductive layer (one or more layers of metal; Metal 3). A first sacrificial layer (e.g., photoresist) is formed and patterned over the patterned conductive layer. The pattern includes via openings. A layer of hinge forming material (one or more layers of metal; Metal 4) is formed over the patterned first sacrificial layer, and patterned to form a torsion hinge (spring) with spring tip extensions and raised address electrodes (FIG. 3). The hinge forming material extends conformally into the via openings to define supports for the hinge (“SP1 Via” in FIG. 3) and for the raised electrodes. A second sacrificial layer (e.g., also photoresist) is formed and patterned over the patterned hinge forming layer. The pattern includes a central via opening. A layer of mirror forming material (one or more layers of metal; Metal 5) is formed over the patterned second sacrificial layer, and patterned to form a reflective element (rectangular-shaped mirror). The mirror forming material extends into the via opening to define a support for the mirror (“Mirror Via” in FIG. 3). To provide flatness, the second sacrificial layer is planarized prior to deposition of the mirror forming material. The first and second sacrificial layers provide support to the hinge and mirror forming layers during fabrication and are subsequently removed (viz., dry etched) to release (“free”) the hinge and mirror following formation.
FIGS. 13-15 illustrate the assembled and released pixel structure of FIG. 3, with the mirror tilted to a 12 deg. tilt angle after setting in consequence of a Reset signal to the “ON” (+12 deg.) or “OFF” (−12 deg.) position in accordance with the logic 1 or logic 0 state previously stored in the underlying CMOS memory cell. Setting the position of each mirror occurs electrostatically. The output of the memory cell (logic 1 or logic 0, corresponding to the bit-plane bit for that pixel position) and its complement control the opposite potentials applied to mirror electrodes located below the mirror on respective sides of the hinge axis. When an appropriate bias/reset potential is applied to the mirror (or mirror/yoke assembly), the mirror tilts about its hinge axis in attraction to the electrode with the greatest potential difference relative to the bias/reset potential. The mirror lands on the spring tips closest to that electrode, preventing contact of the mirror with the electrode and pre-loading the mirror for release under stored energy of spring action. When the bias is removed (allowed to float or set to 0 volts), the mirror returns to a flat state.
A simplified rendition of the logic state loading and position reset operation is illustrated schematically in FIG. 16. Setting the mirror position involves the application of three voltage signals to the pixel: a mirror bias/reset voltage (MBRST), an address voltage Φa, and an address complement voltage Φa. In a typical implementation, the memory cell may be a 5T SRAM memory cell which provides two address nodes: Address Φa (0/3.3 V) and Complement Φa (3.3/0V). The voltages from the address nodes are applied to the raised address electrodes (formed at the hinge level) through the metal address pads (formed at the Metal 3 level) by via contacts (“Via 2 Contact to CMOS”) to the underlying CMOS memory cell structure (see FIGS. 3, 13 and 14). The bias/reset voltage is applied via routing for the pixels of the same common reset block of mirrors on the Metal 2 and Metal 3 layers, to the bias/reset bus elements (see FIGS. 3, 13 and 14), to the hinge through the hinge support vias (“SP1 Vias”), and to the mirror main structure through the mirror support via (“SP2 Via” in FIG. 14).
FIG. 16 shows the mirror in an initial flat-state or parked position, with the mirror bias/reset voltage (MBRST) set to 0 volts. With 0 volts MBRST applied as shown, the logic 0 is applied to the memory cell, which applies an address voltage (Address Φa) of 0 volts to one address electrode and an address complement voltage (Complement Φa) of 3.3 volts to the other address electrode. The bias/reset voltage is then raised to 26 volts, which tilts the mirror about the diagonal hinge axis, away from the address electrode to which the address complement voltage (3.3 volts) is applied and toward the address electrode to which the address voltage (0 volts) is applied. This sets the mirror into a −12 deg. “OFF”-state tilt position as shown in the rightmost, middle view in FIG. 16.
To shift the mirror into the other +12 deg. “ON”-state position involves a similar operation. The logic 1 is applied to the memory cell, which applies an address voltage (Address Φa) of 3.3 volts to the one address electrode and an address complement voltage (Complement Φa) of 0 volts to the other address electrode. The increase from 0 volts to 3.3 volts of the one address electrode and decrease from 3.3 volts to 0 volts of the other address electrode does not affect the potential difference (relative to the 26 volt mirror voltage) significantly enough to move the mirror out of its tilted position, so the mirror remains in its “OFF”-state position for the updated loading of the memory cell and until the application of a Reset pulse to the mirror through the bias/reset bus. When this occurs, the mirror is released to move through the flat-state position into the +12 deg. “ON”-state tilt position as shown in the rightmost, bottom view in FIG. 16.
An example Reset pulse may involve increasing the mirror bias voltage (above 26 volts) for an initial period, then removing the bias voltage for a short period (going to 0 volts or floating the mirror), and then reapplying the bias voltage (26 volts). The initial increase in bias voltage increases the electrostatic attraction between the adjacent address electrode (left electrode in FIG. 16; now at 3.3 volts) and the mirror (now at greater than 26 volts), causing the mirror to be attracted even more toward the adjacent electrode. This greater attraction deforms the spring tips and may also deform the torsion hinge (and hinge yoke, if present) so that, when the Reset pulse is removed, the energy stored by the deformation is released and the mirror springs away from the adjacent electrode (left electrode in FIG. 16; now at 3.3 volts) toward the flat-state position (initial 0 volt position discussed previously). This enables the released mirror to transition from tilting toward the one electrode to tilting nearer to the other electrode on the opposite side of the torsion hinge. After the mirror is repositioned nearer to the other electrode, the bias voltage (26 volts in this example) is reapplied and the mirror is attracted to the other electrode (right electrode in FIG. 16; now at 0 volts) as shown in the rightmost bottom view in FIG. 16.
Additional details and variations regarding the application of voltages to set mirror tilt positions are given in U.S. Pat. Nos. 5,444,566; 5,771,116; 6,480, 177; 6,906,850; 6,985,278; and references cited therein; the entireties of all of which are incorporated by reference herein.